Latency control circuit, semiconductor memory device including the same, and method for controlling latency

ABSTRACT

A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2009-0083441, filed on Sep. 4, 2009, which is incorporated herein byreference in its entirety.

BACKGROUND OF THE INVENTION

The disclosed embodiments relate to a latency control circuit, and moreparticularly, to a technology for increasing accuracy of a latencycontrol circuit.

Diverse semiconductor chips do not operate alone but transfer/receivesignals to/from other neighboring semiconductor chips to operate. Forexample, when a memory controller applies a read command to asemiconductor memory device, the semiconductor memory device transfersdata stored therein to the memory controller. However, the semiconductormemory device cannot transfer its data to the memory controllerinstantly after it receives the read command because time is requiredfor the semiconductor memory device to call for and output the storeddata inside.

For a first semiconductor chip A and a second semiconductor chip B tointeract, it takes a predetermined waiting time for the firstsemiconductor chip A to request the second semiconductor chip B toperform a particular operation, and the second semiconductor chip B toperform the requested operation in response to the request. This waitingtime is referred to as latency. For example, when CAS (column addressstrobe) latency (CL) is set at 7 clocks/clock cycles and the memorycontroller applies a read command to a semiconductor memory device, thesemiconductor memory device transfers data to the memory controller 7clocks after the application time point of the read command.

A circuit for controlling such latency that enables cooperation betweenthe first semiconductor chip A and the second semiconductor chip B isreferred to as latency control circuit.

FIG. 1 illustrates a conventional latency control circuit and itsperipheral units. Referring to FIG. 1, an input signal INPUT inputted toan input pad 101 represents a signal inputted to a semiconductor chip,and a target circuit 140 is a circuit that performs an operation (forinstance, an operation referred to hereinafter as “X” operation) inresponse to the input signal INPUT. Delay A 110 represents a delay thatthe input signal INPUT goes through inside the chip until it arrives ata latency control circuit 120, and delay B 130 represents a delay thatthe input signal INPUT outputted from the latency control circuit 120goes through until it arrives at a target circuit 140.

When it is assumed that the latency between the input signal INPUT andthe X operation is N, the target circuit 140 should perform the Xoperation at N clocks after the input signal INPUT is applied to theinput pad 101. Therefore, the input signal INPUT inputted to the inputpad 101 should arrive at the target circuit 140 exactly at N clocksthereafter. The latency control circuit 120 controls a delay value ofthe input signal INPUT in such a manner that the input signal INPUTarrives at the target circuit 140 at the time corresponding to thelatency accurately.

As described before, the latency control circuit 120 is desired tocontrol the delay value of the input signal INPUT so that the inputsignal INPUT inputted to the inside of the chip arrives at the targetcircuit 140 at N clocks later corresponding to the latency. However,there are many variables. The delay values of the delay A 110 and thedelay B 130 continue to be changed as the process, voltage, andtemperature (PVT) conditions are changed inside the chip. Therefore,there is a concern that the latency control circuit 120 does nottransfer the input signal INPUT to the target circuit 140 at the exacttime corresponding to the latency.

SUMMARY OF THE INVENTION

Some embodiments of the present invention are directed to a latencycontrol circuit that transfers an input signal to a target circuit at anexact time.

Particularly, although the situation inside a chip may be changed due toa change in process, voltage and/or temperature (PVT) conditions, thelatency control circuit makes the input signal inputted to the inside ofthe chip arrive at the target circuit at the exact time.

In accordance with an embodiment, there is provided a latency controlcircuit, which includes: a path calculator configured to calculate adelay value of a path that an input signal is to go through inside achip and output the delay value as path information; a delay valuecalculator configured to output delay information representing a delayvalue for delaying the input signal based on a latency value of theinput signal and the path information; and a delayer configured to delaythe input signal by a delay corresponding to the delay information.

The delay value calculator may be configured to generate the delayinformation by subtracting a value of the path information from thelatency value. The path information and the delay information may eachrepresent a number of clock cycles.

The path calculator may include: a replica delay unit configured to havethe same delay value as a delay value of the path that the input signalis to go through inside the chip, delay a path calculation start signal,and output a delayed path calculation start signal; and a first countingunit configured to count the number of clock activations from a momentwhen the path calculation start signal is enabled to a moment when anoutput signal of the replica delay unit is enabled and output the pathinformation.

In accordance with another embodiment, there is provided a semiconductormemory device, which includes: a path calculator configured to calculatea delay value of a path that a termination command is to go throughinside the semiconductor memory device and output the calculated delayvalue as path information; a delay value calculator configured to outputdelay information representing a delay value for delaying thetermination command based on a write latency and the path information; adelayer configured to delay the termination command by a delaycorresponding to the delay information; and a terminator configured toperform a termination onto an input pad in response to an output signalof the delayer.

In accordance with another embodiment of the present invention, there isprovided a method for controlling a latency of an input signal inputtedfrom outside a semiconductor chip, which includes: generating pathinformation based on a delay value of a path that an input signal is togo through inside the chip and; generating delay information based on alatency value of the input signal and the path information; and delayingthe input signal by a delay corresponding to the delay information andoutputting a delayed input signal.

The delay information may be generated by subtracting a value of thepath information from the latency value.

The calculating of the delay value of the path that the input signal isto go through inside the chip and generating the path information mayinclude: delaying a path calculation start signal by the same delayvalue as the delay value of the path that the input signal is to gothrough inside the chip and outputting a delayed path calculation startsignal; and counting the number of clock activations from a time thatthe path calculation start signal is enabled to a time that the delayedpath calculation start signal is enabled and outputting the pathinformation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a conventional latency control circuit and itsperipheral units.

FIG. 2 is a block view illustrating a latency control circuit inaccordance with an embodiment of the present invention.

FIG. 3 is a block view describing a path calculator 210 of FIG. 2.

FIG. 4 is a timing diagram describing an operation of the pathcalculator of FIG. 3.

FIG. 5 illustrates a delayer 230 shown in FIG. 2 in accordance with anembodiment of the present invention.

FIG. 6 is a block view describing a latency control circuit applied to asemiconductor memory device in accordance with an embodiment of thepresent invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Hereinafter, specific embodiments will be described with reference tothe accompanying drawings. The drawings are not necessarily to scale andin some instances, proportions may have been exaggerated in order toclearly depict certain features of the embodiments.

FIG. 2 is a block view illustrating a latency control circuit inaccordance with an embodiment of the present invention. Referring toFIG. 2, a latency control circuit 200 of the present embodiment includesa path calculator 210, a delay value calculator 220, and a delayer 230.The path calculator 210 calculates a delay value of a path which aninput signal INPUT goes through and outputs the delay value as pathinformation PATH<2:0>. The delay value calculator 220 outputs delayinformation DELAY<2:0> which represents a delay value for delaying theinput signal INPUT based on latency information LATENCY<2:0> of theinput signal INPUT and the path information PATH<2:0>. The delayer 230delays the input signal INPUT by a delay corresponding to the delayinformation DELAY<2:0>.

A target circuit 260 shown in FIG. 2 is a circuit performing anoperation that is directed by the input signal INPUT in response to theinput signal INPUT. For example, when the input signal INPUT is acommand to perform an X operation and the latency of the input signalINPUT is determined to be 7 clocks, the target circuit 260 is a circuitwhich should perform the X operation 7 clocks after the input signalINPUT is inputted into a chip, that is, a moment when the input signalINPUT is inputted into an input pad 201.

The path calculator 210 calculates a delay value of a path which theinput signal INPUT is to go through inside the chip and outputs thedelay value as path information PATH<2:0>. The delay value of a paththrough which the input signal INPUT is to go inside the chip is a valueobtained by summing a delay of an the input signal INPUT through delay A240, and a delay of an input signal INPUT_CONTROLLED through delay B250. In short, the path information PATH<2:0> is a value obtained byquantizing a sum of a delay value of the delay A 240 and a delay valueof the delay B 250 in terms of a number of clock-cycles.

The delay value calculator 220 outputs delay information DELAY<2:0>,which represents a delay value for delaying the input signal INPUT,based on the latency information LATENCY<2:0> and the path informationPATH<2:0> of the input signal INPUT. To be specific, the delay valuecalculator 220 generates the delay information DELAY<2:0> by subtractingthe path information PATH<2:0> from the latency informationLATENCY<2:0>. In short, latency information LATENCY<2:0>−pathinformation PATH<2:0>=delay information DELAY<2:0>. Herein, <2:0>signifies that each of the path information PATH<2:0>, latencyinformation LATENCY<2:0>, and delay information DELAY<2:0> is a 3-bitdata. It is obvious to those skilled in the art that the number of bitsof each information path information PATH<2:0>, latency informationLATENCY<2:0>, or delay information DELAY<2:0> may be different accordingto different schemes. The delay value calculator 220 may be formed of asimple subtraction circuit.

The delayer 230 outputs the input signal INPUT after delaying the inputsignal INPUT by a delay corresponding to the delay informationDELAY<2:0>. To be specific, the delayer 230 outputs the input signalINPUT after delaying the input signal INPUT by a number of clockscorresponding to the number represented by the delay informationDELAY<2:0>. For example, when the delay information DELAY<2:0>represents 4, the delayer 230 delays the input signal INPUT by 4 clocksand outputs the delayed input signal INPUT CONTROLLED.

To have a look at the overall operation, the path calculator 210calculates a delay value of the input signal INPUT that the input signalINPUT is to go through inside the chip and outputs the calculated delayvalue as the path information PATH<2:0>. The delay value calculator 220generates the delay information DELAY<2:0> by subtracting the value ofpath information PATH<2:0> from the value of the latency informationLATENCY<2:0>. Subsequently, the delayer 230 delays the input signalINPUT by a delay corresponding to the delay information DELAY<2:0> andoutputs the delayed input signal INPUT_CONTROLLED. In short, the inputsignal INPUT delayed for a delay corresponding to the delay DELAY<2:0>in the delayer 230 and delayed elsewhere by delays corresponding to asum of DELAY A and DELAY B inside the chip in being communicated to thetarget circuit 260. Thus the input signal INPUT arrives at the targetcircuit 260 exactly after the latency period lapses from the input ofthe input signal INPUT to the input pad 201 of the chip.

Although the delay value inside the chip may be changed due to a changein process, voltage and/or temperature, the latency control circuit 200of the present embodiment measures and reflects the change in the delayvalue, it is possible to make the input signal INPUT always arrive atthe target circuit 260 accurately after the latency period lapses.

FIG. 3 is a block view describing the path calculator 210 of FIG. 2.Referring to FIG. 3, the path calculator 210 includes a replica delayunit 310 and a first counting unit 320. The replica delay unit 310 hasthe same delay value as the delay value of the path that the inputsignal INPUT is to go through inside the chip, and delays a pathcalculation start signal START and outputs the delayed path calculationstart signal SYNC_START. The first counting unit 320 counts the numberof clock CLK activations from a moment when the path calculation startsignal START is enabled to a moment when an output signal SYNC START ofthe replica delay unit 310 is enabled, and outputs path informationPATH<2:0>.

The replica delay unit 310 includes D flip-flops DFF 311 and 313 and areplica delay line 312. The replica delay line 312 is formed based on avalue of the total delay that the input signal INPUT goes through insidethe chip (for example, delays other than a delay through delayer 230 inFIG. 2). When it is applied to the situation of FIG. 2, the replicadelay line 312 has a delay value obtained by summing the delays of thedelay A 240 and the delay B 250. The D flip-flops DFF 311 and 313synchronize the signals START and ASYNC_START with the clock CLK toensure operations at accurate timings but they are not essentialconstituent elements. A signal START inputted to the replica delay unit310 and a signal SYNC_START outputted from the replica delay unit 310have a difference which is the same as the delay that the input signalINPUT goes through inside the chip without a separate delay compensationunit, which is a sum of the delay A and the delay B.

The first counting unit 320 includes a counting element 321 and a codestorage element 322. The counting element 321 counts the number of clockCLK activations in response to the enablement of the path calculationstart signal START and outputs code DCNT<2:0>. The code storage element322 stores the code DCNT<2:0> in response to the enablement of theoutput signal SYNC_START of the replica delay unit 310. Since thecounting of the code DCNT<2:0> starts by the path calculation startsignal START and the code DCNT<2:0> is stored by the signal SYNC_START,the code storage element 322 comes to store the number of clock CLKactivations that corresponds to the overall delay value of the replicadelay unit 310. The code DCNT<2:0> stored in the code storage element322 is outputted as path information PATH<2:0>. Herein, the countingelement 321 is reset when the signal SYNC_START is disabled.

The path calculation start signal START is a signal for initiating anoperation of generating path information PATH<2:0>. When the pathcalculation start signal START is enabled, path information PATH<2:0> isgenerated. The path calculation start signal START may be enabled duringthe initial chip operation, or it may be enabled periodically to updatethe path information PATH<2:0>. Since the generation of the pathcalculation start signal START may be easily implemented by those ofordinary skill in the art to which the present embodiment pertains,further description on it is omitted.

FIG. 4 is a timing diagram describing an operation of FIG. 3. Referringto FIG. 4, at first, a path calculation start signal START is enabled.In response to the enablement of the path calculation start signalSTART, the counting element 321 counts the number of clock CLKactivations and starts to increase the value of code DCNT<2:0>.Subsequently, an output signal SYNC_START of the replica delay unit 310is enabled and then the code DCNT<2:0> is stored as path informationPATH<2:0> at a moment when the output signal SYNC_START is enabled. Thecode DCNT<2:0> is a count output indicating a clock count from a momentwhen the path calculation start signal START is enabled and is stored aspath information PATH<2:0> at a moment when the output signal SYNC_STARTis enabled. Therefore, the path information PATH<2:0> comes to haveinformation corresponding to the delay value of the replica delay unit310, which is a delay value that the input signal INPUT goes throughinside the chip.

FIG. 5 illustrates a delayer 230 shown in FIG. 2 in accordance with anembodiment of the present invention. Referring to FIG. 5, the delayer230 includes a second counting unit 510 and a comparison unit 520. Thesecond counting unit 510 counts the number of clock CLK activations froma moment when an input signal INPUT is enabled. The comparison unit 520enables and outputs an output signal INPUT_CONTROLLED when an outputvalue of the second counting unit 510, which is CODE<2:0>, is the sameas delay information PATH<2:0>.

The second counting unit 510 counts the number of clock CLK activationsfrom a moment when the input signal INPUT is enabled and outputs a codeCODE<2.0>. The comparison unit 520 compares a value of code CODE<2.0>with a value of delay information DELAY<2:0>, and when the two valuesare the same, the comparison unit 520 enables an output signalINPUT_CONTROLLED. Therefore, when clock is activated for a number oftimes equal to the value represented by the delay information DELAY<2:0>after the initial input of the input signal INPUT, the output signalINPUT_CONTROLLED is enabled.

In short, the delayer 230 delays the input signal INPUT by a delay equalto the delay value represented by the delay information DELAY<2:0> andoutputs the output signal INPUT_CONTROLLED. For example, when the delayinformation DELAY<2:0> is 5, the output signal INPUT_CONTROLLED isenabled 5 clocks after the enabling of the input signal INPUT.

A reset RST signal inputted to the second counting unit 510 resets thesecond counting unit 510. Although FIG. 5 presents an embodiment wherethe delayer 230 is formed of the second counting unit 510 and thecomparison unit 520, it is obvious to those skilled in the art that acircuit outputting the input signal INPUT after delaying the inputsignal INPUT by a delay corresponding to the delay informationDELAY<2:0> may be formed differently from the embodiment shown in FIG.5.

FIG. 6 is a block view describing a latency control circuit 600 appliedto a semiconductor memory device in accordance with an embodiment of thepresent invention. Referring to FIG. 6, the semiconductor memory deviceof the present embodiment includes a path calculator 610, a delay valuecalculator 620, a delayer 630, and a terminator 660. The path calculator610 calculates a delay value of a path that a termination command ODTCMDis to pass through inside a chip (for example, delays other than throughthe delayer 630) and outputs path information PATH<2:0>. The delay valuecalculator 620 outputs delay information DELAY<2:0> representing a delayvalue for delaying the termination command ODTCMD based on a value ofwrite latency WL<2:0> and a value of the path information PATH<2:0>. Thedelayer 630 delays the termination command ODTCMD by a delaycorresponding to delay information DELAY<2:0>. The terminator 660terminates an input pad DQ PAD in response to a signal ODTCMD_CONTROLLEDoutputted from the delayer 630.

The termination command ODTCMD is a command inputted to an ODT PAD 601,and the terminator 660 of a semiconductor memory device should perform atermination onto a data input pad DQ PAD when a delay time correspondingto a write latency WL passes from a moment when the termination commandODTCMD is inputted. The write latency WL is defined as a value obtainedby summing an additive latency AL and CAS write latency CWL. A delay A640 shown in the drawing is a delay that the termination command ODTCMDgoes through from a moment when the termination command ODTCMD isapplied to the ODT PAD 601 to a moment when the termination commandODTCMD is inputted to the latency control circuit 600. A delay B 650 isa delay that a termination command ODTCMD_CONTROLLED outputted from thelatency control circuit goes through until the termination commandODTCMD_CONTROLLED is transferred to the terminator 660. Therefore, thepath information PATH<2:0> has information on a delay value obtained bysumming the delays of the delay A 640 and the delay B 650. A D flip-flopDFF 661 is provided to synchronize the termination commandODTCMD_CONTROLLED with a DLL (delay locked loop) clock DLLCLK. Thetermination command ODTCMD_CONTROLLED is synchronized with the DLL clockDLLCLK because the terminator 660 performing a termination onto the datainput pad DQ PAD operates in synchronization with the DLL clock DLLCLK.

FIG. 6 illustrates an embodiment where the latency control circuit 600is applied to a semiconductor memory device and controls the latency ofthe termination command ODTCMD. Since the structure and operation of thelatency control circuit 600 has been described in detail with referenceto FIGS. 2 to 5, further description on them is omitted.

Herein, referring back to FIGS. 2 to 5, a method for controlling alatency will be described in accordance with an embodiment of thepresent disclosure.

The method for controlling a latency includes generating pathinformation PATH<2:0> based on a delay value of a path that an inputsignal INPUT is to go through inside a semiconductor chip (refer to theoperation of the path calculator 210); subtracting a value of pathinformation PATH<2:0> from a value of latency information LATENCY<2:0>of the input signal INPUT (refer to the operation of the delay valuecalculator 220) to generate delay <2:0>; and outputting a delayed inputsignal INPUT_CONTROLLED by delaying the input signal INPUT by anadditional delay corresponding to delay information DELAY<2:0>.

The generation of the path information PATH<2:0> may include delaying apath calculation start signal START by the same delay value as a delayvalue of a path that the input signal INPUT is to go through inside thechip and outputting a delayed path calculation start signal SYNC_START;counting the number of clocks CLK inputted from a moment when the pathcalculation start signal START is enabled to a moment when the delayedpath calculation start signal SYNC_START is enabled.

The outputting of the delayed input signal by delaying the input signalINPUT by a delay corresponding to delay information DELAY<2:0> includescounting the number of clock CLK activations from a moment when theinput signal INPUT is enabled; and when the counting result, which iscode CODE<2.0>, is the same as delay information DELAY<2:0>, enablingthe output signal INPUT_CONTROLLED.

According to an embodiment of the present invention, a delay value of aninput signal is calculated and path information is generated based onthe delay value of the input signal. A latency control circuitcalculates a delay value to be applied to delaying an input signal basedon latency information and path information. Therefore, the latencycontrol circuit delays the input signal for a delay corresponding to thelatency delay exactly. As a result, the input signal arrives at a targetcircuit at exact time, and the target circuit operates at an exacttiming, that is, according to the designed latency period.

Also, according to an embodiment of the present invention, a delay valueof the input signal through a chip is calculated and taken into incomplying with a latency scheme. Therefore, although the process,voltage and/or temperature are changed and the delay value inside a chipis changed, the intended delay through the chip is met accurately.Therefore, operations of the chip are performed accurately in terms oftimings.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1. A latency control circuit, comprising: a path calculator configuredto calculate a delay value of a path that an input signal is to gothrough inside a chip and output the delay value as path information; adelay value calculator configured to output delay informationrepresenting a delay value for delaying the input signal based on alatency value of the input signal and the path information; and adelayer configured to delay the input signal by a delay corresponding tothe delay information.
 2. The latency control circuit of claim 1,wherein the delay value calculator is configured to generate the delayinformation by subtracting a value of the path information from thelatency value.
 3. The latency control circuit of claim 2, wherein thepath information and the delay information each represent a number ofclock cycles.
 4. The latency control circuit of claim 1, wherein thepath calculator includes: a replica delay unit configured to have thesame delay value as a delay value of the path that the input signal isto go through inside the chip, delay a path calculation start signal,and output a delayed path calculation start signal; and a first countingunit configured to count the number of clock activations from a momentwhen the path calculation start signal is enabled to a moment when anoutput signal of the replica delay unit is enabled and output the pathinformation.
 5. The latency control circuit of claim 4, wherein thereplica delay unit includes: a first flip-flop configured to receive andsynchronize the path calculation start signal with the clock; a replicadelay line configured to have the same delay value as the delay value ofthe path that the input signal is to go through inside the chip, delayan output signal of the first flip-flop, and output a delayed outputsignal; and a second flip-flop configured to receive and synchronize theoutput signal of the replica delay line with the clock and output asynchronized signal.
 6. The latency control circuit of claim 1, whereinthe delayer includes: a second counting unit configured to count thenumber of clock activations from a moment when the input signal isenabled; and a comparator configured to enable and output an outputsignal when an output value of the second counting unit is the same as avalue of the path information.
 7. A semiconductor memory device,comprising: a path calculator configured to calculate a delay value of apath that a termination command is to go through inside thesemiconductor memory device and output the calculated delay value aspath information; a delay value calculator configured to output delayinformation representing a delay value for delaying the terminationcommand based on a write latency and the path information; a delayerconfigured to delay the termination command by a delay corresponding tothe delay information; and a terminator configured to perform atermination onto an input pad in response to an output signal of thedelayer.
 8. The semiconductor memory device of claim 7, furthercomprising: a synchronizer configured to synchronize the output signalof the delayer with a delay locked loop (DLL) clock and transfer thesynchronized signal to the terminator.
 9. The semiconductor memorydevice of claim 7, wherein the path information includes information ona delay value obtained by summing a delay value from a time when thetermination command is inputted from outside the semiconductor memorydevice to a time when the termination command is inputted to the delayerand a delay value from a time when the output signal of the delayer isoutput from the delayer to a time that the output signal of the delayeris transferred to the terminator.
 10. The semiconductor memory device ofclaim 7, wherein the write latency is a sum of an additive latency and aCAS write latency.
 11. The semiconductor memory device of claim 7,wherein the delay value calculator is configured to generate the delayinformation by subtracting a value of the path information from a valueof the write latency.
 12. A method for controlling a latency of an inputsignal inputted from outside a semiconductor chip, comprising:generating path information based on a delay value of a path that aninput signal is to go through inside the chip and; generating delayinformation based on a latency value of the input signal and the pathinformation; and delaying the input signal by a delay corresponding tothe delay information and outputting a delayed input signal.
 13. Themethod of claim 12, wherein the delay information is generated bysubtracting a value of the path information from the latency value. 14.The method of claim 13, wherein the calculating of the delay value ofthe path that the input signal is to go through inside the chip andgenerating the path information includes: delaying a path calculationstart signal by the same delay value as the delay value of the path thatthe input signal is to go through inside the chip and outputting adelayed path calculation start signal; and counting the number of clockactivations from a time that the path calculation start signal isenabled to a time that the delayed path calculation start signal isenabled and outputting the path information.
 15. The method of claim 13,wherein the delaying of the input signal by a delay corresponding to thedelay information and outputting of a delayed input signal includes:counting the number of clock activations from a time that the inputsignal is enabled; and enabling an output signal when the countingresult obtained by the counting of the number of clock activations fromthe time that the input signal is enabled is the same as the pathinformation.